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Earlier this year, AMD announced an update to its mobile processor line that we weren’t expecting quite so soon. The company updated its Ryzen 5000 Mobile processors, which are based around Zen3 and Vega cores, to Ryzen 6000 Mobile, which use Zen3+ and RDNA2 cores. The jump from Vega to RDNA2 on the graphics side was an element we had been expecting at some point, but the emergence of a Zen3+ core was very intriguing. AMD gave us a small pre-brief, saying that the core is very similar to Zen3, but with ~50 new power management features and techniques inside. With the first laptops based on these chips now shipping, we were sent one of the flagship models for a quick test.

AMD Ryzen 6000 MobileZen3+ and RDNA2 Equals Rembrandt

Everyone loves a good codename, and the silicon behind these new mobile processors is called Rembrandt, following AMD’s cadence of naming its mobile processors after painters. Built on the TSMC N6 process node, Rembrandt is one of the first products to use this node enhancement and get some additional voltage/frequency benefits of the updated process. Featuring 8 Zen3+ compute cores and up to 12 RDNA2 compute units for graphics, the monolithic Rembrandt die is designed to scale all the way across AMD’s notebook portfolio, from thin-and-light notebooks down at 15 W all the way up to mobile workstation-level performance at 65 W.

For our testing today, we have the Ryzen 9 6900HS, which is in the top tier product line but designed to be a power-optimized product that AMD uses with select partners based on a collaborative design approach. Anything with the HS at the end means that AMD has been involved in the planning, design, and optimization – the goal here is that AMD wants the HS parts, which have been selected from production with the best performance-to-power ratio, as showcasing the Ryzen brand at its best.

New Features

For this new core to move from 7nm Zen3 to 6nm Zen3+, a number of new additions to the microarchitecture have been made. Normally we consider this to be either a simple manufacturing optimization due to the process node change, or something more fundamental to the core when there’s a microarchitectural change. In this case, AMD hasn’t really discussed any specific improvements coming from the smaller process node, instead focusing on improvements made to the SoC as a whole. At the announcement of the hardware, the headline was ’50 improvements relating to power’, and with the hardware launched we now have insight into what a number of these are.

Fundamentally, the base CPU core is the same Zen3 microarchitecture as the previous generation. Clock for clock, AMD is expecting Zen3+ to behave the same as Zen3 in raw performance output/IPC, with the changes being solely at the power level. Fundamentally AMD is saying that a number of the libraries used in the design were power-optimized, while still keeping a high-frequency capability. Normally a power-optimized design kit offers low power and low area at the expense of frequency, so in reality AMD is finding what it considers to be a more optimal point in that spectrum.

AMD highlighted the following as ‘microarchitecture’ enhancements:

• Per-Thread Power/Clock Control: Rather than being per core, each thread can carry requirements
  
• Leakage: Optimized process and design elements updated for better efficiency
  
• Delayed L3 Initialization: Removes the need to wait for L3 to fully wake from an idle state, making it asynchronous
  
• Peak Current Control: Better control of power ramp from idle to peak to reduce stress and save power
  
• Cache Dirtiness Counter: If cache misses are high (workload is bigger than L3), stay in a high power state even when low power is requested to reduce overall power use
  
• CPPC Per Thread: Previously the OS was only aware of workloads per core, now is aware per-thread for finer control
  
• PC6 Restore: Hardware-assisted wake-from-sleep for quick response
  
• Selective SCFCTP Save: Before waking up cores, refer to utilization before PC6 sleep
  
• Enhanced CC1 State: Better sleep control when core is idle
  

With this being a mobile chip, a lot of context here is on power saving and responsiveness when in-and-out of sleep. The concept of keeping cores at a low idle power, or moving to sleep when idle, is all in aid of enabling a device with a long(er) battery life. For example, if a core is idle for a few seconds, would it be better to put in a sleep state? This isn’t just idle frequency, but actually turning parts of the core off in a specific order – and then how and when those parts are turned back on, which has a power cost all of its own – ultimately leading to working smarter in order to conserve power usage.

On the SoC side of power matters, AMD is showcasing that Rembrandt has better control over the internal Infinity Fabric power states, better global ‘almost off’ power states, support for LPDDR5, DRAM self-refresh, panel self refresh support, support for sub-1W panels, and accelerators to help come back out of sleep states, some of which we’ve mentioned.

On the firmware and software side, AMD is aiming to make Rembrandt a better transitional experience from being connected to power to being a mobile platform. Normally Windows relies on internal power plans for ‘Balanced’, ‘High Performance’, or ‘Battery Saver’ – sometimes OEMs even have their own unique power plans on top of their own software. From AMD’s perspective, they want users to have the benefits of both High Performance and Battery Saver without having to manually adjust these power plans. Which brings us to AMD’s new Power Management Framework, or PMF.

PMF is an extension of a lot of previous notebook inputs, outputs, and controls – taking data from sensors such as skin temperature, but also SoC power, OS workloads, display information, noise profiles, then converting that into a ramping power profile that can offer anything from battery saver to high performance on a sliding scale.

The key here is that graph – normal Windows offerings have those individual three points, whereas AMD Rembrandt, on select optimized systems, will enable by default a scalable profile that will move up and down the graph depending on external factors. When speaking to AMD, they said that this would be baked into the firmware and automatically enabled when running in the Windows-standard Balanced Profile. User can manually select other profiles to force into those modes, but Balanced Profile will be the PMF sliding scale.

Users will not be able to disable PMF, but more than that, AMD states that it is up to the system vendor to announce if they are using PMF or not. Given that it's likely that few (if any) of them will bother to make that disclosure, I think this is somewhat of a frustrating decision – we can’t test this without a lever to disable it, whereas end-users won’t know if their system even has it or not.

Finally, AMD lists its updates for Rembrandt in the display power section of the chip. As we move to more efficient processors coupled with high-resolution, high refresh rate panels, the power consumption of the panel is becoming a major factor. But part of it is down to the SoC inside.

We’ve already mentioned Panel Self Refresh, the ability for a panel to update only the section that has actually changed from frame to frame, but AMD is saying that they can also do this with Freesync enabled. On top of this, Freesync allows the refresh rate during video fullscreen playback to be reduced to the native framerate of the video (e.g. 23.976Hz), thus saving power. The sub 1-watt panel support means that AMD has a list of validated panel vendors that can provide lower power panels (typically 1080p at 300 nits) for long battery life designs. Physically the new chip also implements new SVI3 regulators, which AMD claims provides a faster and more discrete control over the voltage required from the chip.

On top of this is the graphics engine itself, Rembrant moves from a Vega 8 solution to an RDNA2 solution, offering more performance and better efficiency. This extends to AMD A+A Advantage support as well, offering advanced power control when paired with an AMD discrete graphics solution.
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