PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec

[harlan4096]

Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0’s bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.

Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison’s sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.

The fastest standard on the PCI-SIG roadmap for now, PCIe 5.0’s higher transfer rates will allow vendors to rebalance future designs between total bandwidth and simplicity by working with fewer lanes. High-bandwidth applications will of course go for everything they can get with a full x16 link, while slower hardware such as 40GigE and SSDs can be implemented using fewer lanes. PCIe 5.0’s physical layer is also going to be the cornerstone of other interconnects in the future; in particular, Intel has announced that their upcoming Compute eXpress Link (CXL) cache coherent interconnect will be built on top of PCIe 5.0.

Meanwhile the big question, of course, is when we can expect to see PCIe 5.0 start showing up in products. The additional complexity of PCIe 5.0’s higher signaling rate aside, even with PCIe 4.0’s protracted development period, we’re only now seeing 4.0 gear start showing up in server products; meanwhile the first consumer gear technically hasn’t started shipping yet. So even with the quick turnaround time on PCIe 5.0 development, I’m not expecting to see 5.0 show up until 2021 at the earliest – and possibly later than that depending on just what that complexity means for hardware costs.

Ultimately, the PCI-SIG’s annual developer conference is taking place in just a few weeks, on June 18th, at which point we should get some better insight as to when the SIG members expect to finish developing and start shipping their first PCIe 5.0 products.

Continue Reading

[harlan4096]

PCI Express 4.0 motherboards, Solid State Drives. and other devices are not widely available yet, but that has not stopped the Peripheral Component Interconnect Special Interest Group (PCI-SIG) from releasing PCI Express 5.0 specifications on May 29, 2019.

Compared to PCI Express 4.0, PCI Express 5.0 promises double the bandwidth and other improvements while maintaining backwards compatibility with existing PCI Express peripherals.

PCI Express 4.0 doubled the bandwidth, frequency, and transfer rate of PCIe 3.0, and PCI Express 5.0 is designed to quadruple it.

Target markets for PCI Express 5.0 include gaming, visual computing, AI, storage, and machine learning.

The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.

Tools like HwInfo or CPU-Z may help you find out which PCI Express standards the PC you run this on supports (if any).

PCI Express 5.0 specification details

* Bandwidth of 128 GB/s, 32 GT/s, 32.0 GHz frequency, and 128b/130b encoding.
* Backwards compatible with all major PCI Express standards (4.0, 3.x, 2.x, and 1.x).
* Features new backwards compatible CEM connector for add-in cards.
* Support for extended tags and credits.
* Electrical changes improve signal integrity and mechanical performance of connectors.

Continue Reading