After Stacked L3, AMD Is Now Exploring Ways To Stack Even The L2 Cache On Its Future

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In a new research paper, AMD is exploring ways to stack L2 cache on its future chips, offering similar or better latency.

3D V-Cache But For L2: AMD Exploring Integrating Stacked L2 Caches Besides L3 For Future Chip

sAMD has published an interesting research paper titled "Balanced Latency Stacked Cache" with a patent application number of "US20260003794A1". In this paper, AMD discloses techniques for a balanced latency stacked cache, where a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die.



We know that AMD already offers stacked cache in the form of 3D V-Cache, which employs an additional L3 cache layer, either on top or underneath its core compute chiplets. The first generation of 3D V-Cache was stacked on top of Zen compute chiplets, while the second generation saw the placement of the stack below the compute chiplet. These approaches are largely similar in the premises, as they both use a stack cache layer.

AMD's 3D V-Cache or X3D solution has been used on chips ranging from the client "Ryzen" series to the top-tier datacenter powerhouses such as the "EPYC" lineup. While AMD continues to develop its L3 3D V-Cache technologies, the company is exploring more ways to stack further caches. The patent points to L2 stacks being the red team's next venture.
 
Image Source: AMD Patent

For its stacked L2 cache design, AMD uses an illustrative example, showcasing a base die that is attached to a compute die and a cache die, and then a further compute and cache die is added on top of it. This example uses a cache module with four 512 KB regions for a total of 2 MB L2 cache, and a CCC or Cache Control Circuitry. This L2 cache complex can be expanded as needed with up to 4 MB showcases in the block diagram.

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