Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL

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Ever since Intel purchased Altera for an enormous amount of money a few years ago (ed: $16.7B), the FPGA portfolio that has been coming out has largely been a product of the pre-Intel days. Today however that changes, as Intel is announcing its first fully Intel-designed FPGA, built upon its own internal 10nm process, with the Agilex brand name. This new range of products is set to roll out later this year for sampling, and offer a mix of analog, digital, memory, custom IO, and eASIC variations within a singular platform.

For users familiar with Intel’s FPGA family, the new Agilex portfolio is a generational upgrade over the current Stratix 10 family. The new Agilex parts, according to Intel, offer up to 40% higher performance or 40% lower power, up to 40 TFLOPs of DSP performance, and support for all the latest and future technologies. It’s this latter part that becomes important as the role of the FPGA is transmogrifying into a general purpose design platform into an optimized compute platform.

The Agilex FPGA builds on similar design principles to the Stratix – a centralized FPGA block of gates with hardened features and external connections out to several different technologies, based on the customer requirements. For these external connections, Intel is using its Embedded Multi-Die Interconnect Bridge (EMIB) technology, which in the examples given can be expanded into other chiplets. Some of the chiplet suggestions from Intel include High Bandwidth Memory (HBM), next-generation 112G transceivers, PCIe Gen 5.0 root complexes, Compute eXpress Link interfaces (through PCIe 5.0), additional CPU cache coherent interconnects, and other chiplets/IP as determined by the customer. To add into all of this, Agilex will also support Intel’s Optane DC Persistent Memory.

One of the big updates to the FPGA family comes through Intel’s recent acquisition of eASIC. Intel has actually been working with eASIC for several years, however in 2018 it purchased the company outright to deliver additional synergies into its programmable product portfolio. With Agilex, the first stage of this vision is set to be delivered – customers that want quick IP deployment can choose to work with Intel’s eASIC division for chiplet IP deployment or fusion into the FPGA, quicker than the customer is able to do themselves, and taking advantage of Intel’s own product design chain.

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