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Ryzen 4000 Detailed: Purported AMD Confidential Documents Outline Zen 3's Inner Worki
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[Image: rCiXwPTcMSwJqsP8z2SLnf-970-80.jpg.webp]

A teaser before October 8.

While we wait for AMD's Zen 3 announcement on October 8, hardware leaker CyberPunkCat has just sent us a sneak preview of what's to come. AMD's processors already occupy five of the six positions in our Best Gaming CPUs list, and Zen 3 will likely solidify AMD's position even more.

The document, which dates back to June 10, appears to come from AMD's secret vault. While the information looks legit, we still recommend you approach it with a bit of caution. However, the info does align with what we already know about the Zen 3 microarchitecture for an accidentally-posted AMD presentation. 

With that in mind, the document is a Processor Programming Reference (PPR) guide for AMD's Family 19h Model 21h B0. As a refresher, Zen(+) and Zen 2 belong to Family 17h, so Family 19h should be for Zen 3.

Little surprise, Ryzen 4000-series (codename Vermeer) processors will retain the multi-chip module (MCM) design, otherwise known as a chiplet design. Zen 3 will package two core complex dies (CCDs) with a one I/O die (IOD) inside of a chip package. On the outside, the setup looks identical to Zen 2, but it's not. The devil is in the details.

On Zen 2, each CCD houses two core complexes (CCXs), whereby each complex is comprised of four cores that share 16MB of L3 cache. According to the AMD document, Zen 3's composition is completely different - there's only one CCX inside each CCD. The CCX possesses eight cores that can either run in single-thread (1T) or two-thread SMT (simultaneous multithreading) mode (2T), amounting up to 16 threads per complex. Since there's only one CCX now, all eight CPU cores can now directly access the 32MB of shared L3 cache.

Essentially, the amount of L3 cache remains the same at 32MB per CCD on Zen 3 as on Zen 2. On Zen 2, the four cores inside each CCX only have direct access to 16MB of L3 cache whereas on Zen 3, all eight cores within the CCX share the same 32MB of L3 cache. The revamped design should lower latency substantially and improve overall instruction per cycle (IPC) on Zen 3 parts.

In terms of core counts, Zen 3 seems to paint a similar picture as Zen 2. The flagship Ryzen 4000-series part, potentially the Ryzen 9 4950X , will likely max out at 16 cores and 32 threads, just like existing Ryzen 9 3950X. However, you can expect improved clock speeds on Zen 3 as early engineering samples of the Ryzen 9 4950X purportedly already boost up to 4.9 GHz when the previous Ryzen 9 3950X tops out at 4.7 GHz.

As per the information inside the document, Zen 3 features two unified memory controllers (UMC), one per channel. Each channel supports up to two DIMMs.

There is also mention of the scalable data fabric with the capacity to handle up to 512GB for each DRAM channel. In regards to memory speeds, Zen 3 processors arrive with native support for DDR4-3200, in the same vein as Zen 2. 
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