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TSMC Preps for 3nm Risk Production
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[Image: inWCPzXNVFbyYDRmxtthn3-1024-80.jpg.webp]

TSMC confident in semiconductor demand, economy recovery.

Taiwan Semiconductor Manufacturing Co. said this week that it would significantly increase its capital expenditures this year as it needs to build and equip new fabs to ramp up its existing and next-generation leading-edge process technologies. Demand for advanced fabrication nodes is on the rise. In Q4 2020, revenue for N5 (5 nm) and N7 (7 nm) technologies accounted for nearly half of TSMC's revenue, so it makes a great sense for the manufacturer to continue investing in leading-edge capacities. Furthermore, as Apple and Intel plan to increase orders to TSMC, the foundry will also need more capacity.

TSMC to Spend Up to $28 Billion on Production Facilities in 2021

TSMC's management plans to spend from $25 billion to $28 billion on capital expenditures in 2021, the world's largest contract maker of semiconductor announced this week. 

If TSMC's board approves all the investments proposed by the management, then TSMC's CapEx will rise by 45% ~ 62% year-over-year from $17.2 billion in 2020. The lion's share of TSMC's capital budget will be spent on expanding production capacities for the company's N5 and N7 nodes as well as equipping a leading-edge fab for its N3 (3 nm) node that will be used starting from the second half of 2022. 

"Out of the $25 to $28 billion CapEx for 2021, about 80% of the capital budget will be allocated for advanced process technologies, including 3 nm, 5 nm and 7 nm," said Wendell Huang, chief financial officer at TSMC, during this week's earnings call with analysts and investors. "About 10% will be spent for advanced packaging and mask making and about 10% will be spent for speciality technologies." 

"The 2021 CapEx is largely for N5 expansion (at least 2x its current 55-60k WPM capacity), and N3 build is limited to pilot line/initial production (+10-15k WPM, though we expect N3’s capacity to be similar to N5’s upon full ramp-up)," Szeho Ng, an analyst with China Renaissance Securities, wrote in a note to clients on Friday.

Production of semiconductors is an extremely capital-intensive business and as process technologies get more advanced and manufacturing tools get more expensive, chipmakers have to increase their CapEx budgets to build fabs that cost as much as $20 billion or even more. Because of increasingly high R&D and fab costs, numerous contract makers of semiconductors had to pull out from the leading-edge and focus on specialized technologies in the recent years.

N5 & N7 Accounted for 49% of TSMC's Revenue in Q4 2020

But with a number of rivals out of the game, TSMC now has more clients than ever. And considering the fact that there are a number of ongoing megatrends — such as 5G, AI, high-performance computing (HPC), and edge computing — that require advanced chips produced using the most sophisticated technologies possible, demand for TSMC's higher-end production services is on the rise today and will continue growing in the coming years.   

In the fourth quarter, sales of wafers processed using N5 accounted for 20% of TSMC's total wafer revenue, whereas sales of N7 and 12 nm/16 nm accounted for 29% and 13% respectively. In general, leading-edge N5 and N7 nodes commanded 49% of TSMC's wafer revenue, whereas advanced nodes (N5, N7, N12/N16) accounted for 62% of the company's total wafer revenue. 

TSMC's N5 process technology in Q4 2020 was primarily used by Apple, which uses it for its A14 system-on-chips for smartphones and tablets as well as M1 SoCs for its latest PCs. The company's N7 is used more widely by companies like AMD, Apple, Nvidia, Qualcomm, and Xilinx, whereas N12/N16 is used by dozens of companies for all kinds of applications.  

"Our fourth quarter business was supported by strong demand for our industry-leading 5 nm technology, driven by 5G smartphone launches and HPC-related applications," said Mr. Huang. "Moving into first quarter 2021, we expect our business to be supported by HPC-related demand, recovery in the automotive segment, and a milder smartphone seasonality than in recent years." 

TSMC's N5 is a major improvement over N7 node that enables a 15% higher performance (at the same power and complexity) or a 30% lower power consumption (at the same frequency and complexity), and an up to 1.8X higher transistor density (not for all structures). In addition, N5 uses extreme ultraviolet (EUV) lithography on more than 10 layers to reduce mask count to 81 as well as reduce or even avoid usage of multipatterning, which optimizes yields and costs. Considering all the advantages that N5 has over N7, the majority of TSMC's clients that use N7 now will migrate to N5 over time. 

Later this year TSMC will offer its customers a performance-enhanced version of N5 that is called N5P. The latter is projected to enable a 5% performance gain and/or a 10% power reduction over N5 while staying generally compatible. Yet, N5P will be used by select chip designers only as next year TSMC will offer N4 that will provide further PPA (power, performance, area) enhancements while being compatible with N5 on design rules, IPs, and SPICE levels. TSMC's fabs that currently process wafers using its N5 technology will also be able to use N5P as well as N4, so any investments going there will be used for years.
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