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I Ran Off with Intel’s Tiger Lake Wafer. Who Wants a Die Shot?
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One of the surprises at CES from Intel was the presence of Tiger Lake, Intel’s next generation platform beyond Ice Lake. Tiger Lake is Intel’s vehicle for delivering the first generation of its Xe-LP graphics in a mobile form factor, and there has been a lot of buzz around what Tiger Lake exactly is. We learned this week that it is built on a 10nm+ process, which is different to the ‘10nm’ Ice Lake process (and don’t ask about what Cannon Lake was). Intel has also promoted that Tiger Lake will have higher performance than Ice Lake, both in CPU and graphics, and come with the next generation AI features. Tiger Lake will be out by the end of 2020, but the thing that surprised us most at CES 2020 was the presence of a Tiger Lake wafer.

With a wafer, we can do a few things. With the right angle, we can determine how many die there are on the wafer, and by correlation, the die size. Here’s a good photo taken of the wafer, which we can count the die horizontally and vertically.

In this photo, we can count the die at the widest points of the 300mm wafer. Very rarely to ‘exact numbers of die’ on a wafer, because the reticle is moved to maximize the number of whole die. This is the case here, as we see at the edges ‘half’ die. But for the purposes of die size calculations, we have to take those into account. By sheer luck, in both the x and y dimensions, the two die on the edges come to almost exactly a whole die. This gives us dimensions of 22 die in one direction and 28 die in the other, or 13.64 mm by 10.71 mm, creating a die size of around 146.1 mm2.

Calculating die size is relatively easy in this regard. Actually getting a die shot showing features of the silicon is much harder. Luckily, I spend enough time with the wafer to get that as well.

There are the obvious structures – in the middle we have four cores, on the left is some of the IO logic, on the top right is the Thunderbolt part of the silicon, and on the main right hand side is the Xe graphics.

Current leaks point to Tiger Lake being a quad-core CPU with 96 execution units. Now we know already from Intel’s disclosures that an Xe graphics unit is different to a Gen graphics unit, with an Xe unit capable of doing SIMT work (working on data on its own) individually or SIMD work (wider vector units) collectively by switching modes through software. We confirmed through Raja Koduri that there is no physical difference between the SIMT and SIMD units, and that they operate in this way.

So the quad core we can confirm. For the GPU section, can we actually see 96 execution units? Well, with this first image, I can theroretically see more, however, as we go through the motions, the assumptions are flawed based on this single image alone.

Now this image is hard to make out, but it looks like an Xe unit on its own is very small. It’s very easy to count how many units we have in the top row: 8. In order to reach 96, we would then need to count 12 in the other dimension, however that dimension doesn’t seem to split into 12 evenly. It’s very faint, but we can see that an Xe execution unit is actually quite thin. The effect is easily seen in the top right corner and the bottom right corner, but you can clearly see a unit being thinner in this dimension. How many units do we have in this dimension exactly? I can count 30. It’s fairly easy to see the first five, slightly hardware for the next 5, and then extrapolating that distance down to the end is an effective 3x, making this full GPU block consist of 8x30 units. That makes 240 units.

However, this assumes that the block is just a regular array of execution units. We know this not to be the case. Through additional photos, I noticed that the graphics block had a lot of structure, and it isn’t just a regular array.
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